The present invention relates in general to integrated circuits and, more particularly, to comparator circuits used in programmable analog arrays.
Programmable analog arrays are integrated circuits that include a plurality of programmable analog cells for performing analog signal processing operations such as amplifying, filtering, etc., on analog signals. The analog signals are transferred among the programmable analog cells on programmable interconnect paths formed in routing channels between adjacent cells.
Programmable analog cells and other analog circuits often have a need to determine whether an analog signal has a magnitude greater than a reference or another analog signal. These determinations typically are made using comparators. In circuits such as analog to digital converters where small voltage differences must be resolved to produce a large digital output signal, a high gain is needed. As a result, the comparators often are configured with positive feedback to operate as a latch, which provides the ability to store the comparison result for later use. The accuracy of the comparison is limited by the accuracy of the comparator.
Because a latch retains its previous state, it must be reset before another comparison can be made. Prior art comparators reset the latch after removing its power supply. However, when power is removed, charges stored from a preceding comparison can be trapped on nodes of the comparator. The trapped charges unbalance the comparator and cause comparison errors during a subsequent comparison cycle.
Hence, there is a need for a circuit and method of comparing analog signals which conserves power but which does not result in charges being trapped to unbalance the comparator and produce comparison errors.